1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly relates to a semiconductor integrated circuit device provided on an SOI substrate.
2. Description of the Background Art
In a current semiconductor integrated circuit device (LSI) having a plurality of circuit sections with different functions, such as an input/output circuit (I/O) section, a logic circuit section and a memory section, a configuration is adopted where a plurality of voltages are supplied from external power supplies.
For example, an LSI with two power supplies has been used in relatively many practical uses, in which a 3.3 V power supply is used for the input/output circuit section and a 1.2 V power supply is used for a core circuit section corresponding to core portions of the LSI such as the logic circuit section and the memory circuit section.
Here, a structure (a gate length and a thickness of a gate insulating film) of a MOS transistor included in each of the circuit sections that constitute the LSI differs depending upon a power voltage, and a channel width of the MOS transistor also differs depending upon the circuit section.
For example, in the MOS transistor in the input/output circuit section using the 3.3 V power supply, the channel width is set to not less than 100 μm. This is because, as disclosed in Japanese Patent Application Laid-Open No. 2000-349165 (FIG. 3), the MOS transistor in the input/output circuit section is required to have excellent noise resistance.
On the other hand, in the core circuit section such as the logic circuit section and the memory circuit section, the channel width is set to the order of several μm for the purpose of improving a package density.
As thus described, the input/output circuit section and the circuit section are significantly different in MOS transistor structure. In particular, the MOS transistor constituting the input/output circuit section has been required to have a long channel width. However, in order to respond to such a requirement by only one gate electrode, a length of the gate electrode in the channel width direction would naturally become not less than 100 μm.
Here, the input/output circuit section is provided along the end edge of the LSI due to the nature of its function. The shape of the provided region in a plan view is often slim rectangular, and the length of the gate electrode of the MOS transistor in the channel width direction cannot be made longer without restriction.
Therefore, a configuration has been adopted where a plurality of gate electrodes having the same length are provided in parallel and a plurality of MOS transistors are connected in parallel in place of one MOS transistor having one long gate electrode.
In this case, a total of lengths (referred to as finger lengths) of a portion on an active region (here, SOI layer) of each of the gate electrodes is a channel width. The finger lengths of the plurality of gate electrodes are set so as to correspond to a channel width of one MOS transistor having one long gate electrode.
For example, in a case where a MOS transistor having a channel width of 100 μm is required, restriction on area has been avoided by aligning two MOS transistors in parallel each having a finger length of 50 μm or aligning four MOS transistors in parallel each having a finger length of 25 μm.
As thus described in the input/output circuit section of the conventional LSI, the structure of the MOS transistor was determined only on ground of restriction on area, and this is because a bulk device, which is a semiconductor device formed directly on a silicon substrate called bulk substrate, was a subject to be obtained. On an SOI device which is currently mainstream, there are restrictions as described below.
Namely, a semiconductor device formed on an SOI (silicon on insulator) substrate, so-called SOI device, which is provided sequentially with a buried oxide film and an SOI film has a characteristic of being capable of reducing a parasitic capacitance so as to perform a stable operation at high speed with low power consumption, and has been in use for mobile devices.
One of examples of the SOI device is an SOI device with a full trench separation (FTI) structure where elements are electrically isolated by a full trench isolation insulating film formed by providing a trench reaching the buried oxide film within the surface of the SOI layer and then burying an insulator into the trench.
However, there have been a variety of problems generated by a substrate floatation effect, including a problem in that carriers (holes in NMOS) generated by a collisional ionization phenomenon remain in a body region including a channel formation region, thereby to cause generation of a kink, reduction in operating withstand voltage, and generation of dependency of delayed time on a frequency due to an unstable potential of the body region.
With this being the situation, a partial trench isolation (PTI) structure was contrived as disclosed in Japanese Patent Application Laid-Open No. 2000-243973 (FIGS. 1 to 3). This structure has a partial trench isolation insulating film formed by forming a trench within the surface of the SOI layer such that the SOI layer with a prescribed thickness remains between the bottom of the trench and a buried oxide film and then burying an insulator into the trench.
Adoption of the PTI structure allows shift of carriers through a well region in the lower portion of the partial trench isolation insulating film so as to prevent the carriers from remaining in the body region, and also allows fixing of a potential of the body region through the well region. Accordingly, the variety of problems caused by the substrate floatation effect are not generated.
In the case of adopting the PTI structure, typically, a high density impurity region of the same conductivity type as that of the body region is provided as a body contact region within the surface of the SOI layer on the outside of the end of the gate electrode in the gate width direction, and the body contact region is electrically connected to a wiring layer as an upper layer, to fix a potential of the body region.
However, in the case of adopting the PTI structure, when the channel width of the MOS transistor is increased without restriction, the body region under the gate electrode becomes longer, resulting in that body resistance increases to make it difficult to fix a potential of the body region, leading to a problem of deterioration in transistor characteristic caused by the substrate floatation effect.
As thus described, there has been a problem in the SOI device with the SOI structure adopted therein in that the length of the MOS transistor in the channel width direction cannot be increased from the aspect of suppressing deterioration in transistor characteristic, and it has not been possible to solve the problem by a conventional design index of arranging gate electrodes in parallel to avoid restriction on area.